1. Field of the Invention
This invention relates to a shift register which is useful for a system such as a display panel etc. which requires power saving including a shift register.
2. Description of the Related Art
In an image display apparatus which was configured such that pixels with light emitting devices etc. are arranged in a two-dimensional manner, in order to generate sampling pulses for taking in input serial data (information), for example, a shift register as shown in FIG. 8 is used. This is of such a simple structure that a scanning start signal SSP and a clock signal CK are inputted, and N pieces of registers (D type flip flop (hereinafter, abbreviated as DFF)), and the clock signal CK is inputted to all clock inputs of each DFF, and a Q output of each DFF is connected to a D input of a next stage DFF, and N pieces of sampling pulses SP(1) to SP(N) from a Q output of each DFF.
FIG. 9 is a time chart showing operations of a shift register of FIG. 8. When it is arranged that H level of the scanning start signal SSP simply includes a first ↑ timing of the clock signal CK, it is possible to generate a first sampling pulse SP(1) between the first ↑ timing and a second ↑ timing of the clock signal CK. And, by the clock signal CK which is inputted sequentially, sampling pulses of SP(2) and upward are generated, and a last sampling pulse SP (N) is generated between a Nth ↑ timing and (N+1)th ↑ timing of the clock signal CK. Therefore, (N+1) pieces of ↑ timings of the clock signal CK are required so as to generate N pieces of sampling pulses.
FIG. 10 indicates a circuit structure of DFF which is used. DFF is configured by a clock buffer, a master latch and a slave latch.
The clock buffer comprises two inverters in which input clock Kin is made as a positive clock ck and a negative clock nck, and in FIG. 10, it is configured by M1 to M4.
The master latch is configured by two switches which are configured by M5/M6 and M7/M8 and two inverters which are configured by M9/M10 and M11/M12. The slave switch is configured by two switches which are configured by M13/M14 and M15/M16 and two inverters which are configured by M17/M18 and M19/M20. And an inverter which is configured by M23/M24 is one for outputting a positive output Q.
Further, in all drawings, C and G which are described mainly at a drain terminal of a transistor which configures an inverter designate power supply VCC and a GND terminal, respectively.
<Power Consumption of Shift Register>
Power consumption of DFF in FIG. 10 will be described. Power consumption of a MOS circuit is generated by charging and discharging capacity which is added to a node of a push-pull circuit which is represented by an inverter and which comprises P type transistors and N type transistors. Capacity of the MOS circuit is mainly caused by channel capacity Cox which is generated between a gate oxide film and a channel. Here, simply, a switch circuit in which a gate is of low impedance (push-pull output) and an inverter circuit have the same load capacity Co. Therefore, load capacity that clock series Kin, ck, nck have to drive is 6Co, and power consumption P1 due to clock drive by a clock with a period T0 is obtained by the following equation.P1=VCC2×5Co/To
Power consumption P2 which is required for driving of the clock input CK is obtained by the following equation.P2=VCC2×Co/To
Power consumption which is required for drive of D and Q series may be once charged and discharged for time of (N+1)×To. Therefore, power consumption P3 which is required for drive of D and Q series of a DFF circuit is obtained by the following equation.P3=VCC2×6Co/{To×(N+1)}
Therefore, power consumption Pw1 of a shift register in FIG. 8 is obtained by the following equation (1) assuming that ratio of a period in which the clock CK to all periods is inputted is an operation period ratio K.Pw1=N×(P1+P2+P3)×K  (1)
As a system which uses this shift register as shown in FIG. 8, there is a display panel for displaying images. In the display panel, there are a liquid crystal panel in which a passing light emission amount is controlled by voltage applied of a liquid crystal element of each pixel, and an EL panel using EL (Electro-Luminescence) elements in which a light emission amount can be controlled in response to an amount of a current injected which is injected into each pixel.
Also, as a document for disclosing a structure of a shift register, JP-A-10-74060 is known.